Micro-program control system

ABSTRACT

A micro-program control system for computing apparatus provides a time shared concurrent utilization of a fixed, or semi-fixed memory containing a plurality of micro-programs. Microinstructions of each micro-program are read out in repetitive, sequential manner from the memory and entered into control registers associated with the respective micro-programs. During the time interval in which a micro-instruction of one microprogram is read out, executed and the next address for that micro-program determined, a micro-instruction for another microprogram is read from the memory for implementation. Both the utility of the memory, and the speed of the overall data processing, are thereby improved.

United States Patent Kitamura Sept. 5, 1972 [54] MICRO-PROGRAM CONTROLSYSTEM 3,325,788 6/1967 Hack] ..340/ 172.5

[72] Inventor. Takuo Kitamura, Tokyo, Japan Primary Examiner paul JHenon Assigneei pp Electric Tokyo, Assistant ExaminerMark Edward NusbaumJapan Attorney-Sandoe, Hopgood & Calimafde [22] Filed: Nov. 23, 1970[57] ABSTRACT [2]] Appl. No.: 91,810

A micro-program control system for computing apparatus provides a timeshared concurrent utilization [30] Foreign Appumuon Priority Data of afixed, or semi-fixed memory containing a plurality Nov. 24, 1969 Japan.A4/94068 of -p Micro'instl'ultions of each microprogram are read out inrepetitive, sequential manner 52] us. Cl ..34o/172.5, 444/1 from thememory and entered into control registers [51] Int. Cl ..G06t 9/19associated with the respective micro-programs During [58] Field ofSearch .340] 1725; 235/157; 444/1 the time interval in which amicro-instruction of one micro-program is read out, executed and thenext ad- [56] References Cited dress for that micro-program determined,a micro-instruction for another micro-program is read from the UNITEDSTATES PATENTS memory for implementation. 3,401,376 9/1968 Barnes et al...340/172.5 Both the utility of the memory, and the speed of the3,551,895 12/1970 Dnscoll ..340/172.5 overall data Processing, arethereby improved 3,533,075 10/1970 Johnson et al ..340/l72.5 3,202,9699/ 1966 Dunwell et al ..340/ 172.5 11 Claims, 5 Drawing FiguresArithmetic Unit Arithmetic Arithmetic Unit Unit Ternary Ring CounterPulse Generator Switching Gale \lB Fixed or Semi-fixed Memory Address 2Register Sequential Control Unit MICRO-PROGRAM CONTROL SYSTEM DISCLOSUREOF THE INVENTION This invention relates to computing systems and, morespecifically, to a micro-program control system for use in informationprocessing arrangements.

A micro-program control system refers to a class of systems whereincontrol of arithmetic, logic, or other operations performed by aninformation processing system is implemented by micro-programs, eachcomprising difierent sequences of basic micro-operations. That is,micro-instructions are stored in a fixed or semifixed memory forsubsequent read out and execution in accordance with the respectivemicroprograms. Such a control system has a number of advantages, e.g.,it is simple in arrangement and fabrication, and is readily susceptibleto change in design. However, when compared with a wired logic controlsystem formed solely of electronic logic circuitry, a micro-programcontrol system suffers the following drawbacks:

I. Where the sequence of control is subject to change, that is where aconditional jump or transfer is selectively effected depending upon theresult of previous arithmetic operations, the conditional jump of amicroprogram requires a relatively prolonged period of time for completeexecution. Thus, at such times, micro-program control systems exhibitlow control efficiency, i.e., they slow down a computing process belowthe cycle time capability of the fixed or semi-fixed memory. High speedmemory operation,attainable with recent semiconductor integrated circuitdevelopment and associated technologies, cannot therefore be efficientlyutilized.

2. An appreciable storage capacity is required for a typical memorywhich stores micro-programs. Should an increased demand be placed uponthe performance of such micro-programs, as to perform complex operationsby utilizing a micro-program requiring a great number ofmicro-instructions, even greater fixed or semi-fixed memory capacitywould be necessary. The micro-program memory would then become a majorcontributor to the total cost of a computing system, and this may not beeconomically realistic.

It is therefore an object of this invention to provide a micro-programcontrol system which substantially improves the utilization of a fixedor semi-fixed memory which stores micro-programs, and which thusimproves control efficiency.

It is another object of the invention to provide a micro-program controlsystem which permits relatively efficient utilization of a memorycontaining a microprogram when a conditional jump or transfer is to beeffected.

It is a further object of the invention to provide a micro-programcontrol system wherein a memory, capable of storing a great number ofmicro-programs, is operated on a relatively inexpensive basis inrelation to the computational efficiency effected.

[t is still another object of the invention to provide a micro-programcontrol system which effectively uses the high speed performance of asemi-fixed memory formed by semiconductor integrated circuit techniques.

It is still a further object of the invention to provide a micro-programcontrol system in which a fixed or semifixed memory, storingmicro-programs, is utilized for simultaneously implementing and using aplurality of micro-programs.

The above and other objects of the present invention as realized in aspecific illustrative digital processing arrangement wherein a singlefixed or semi-fixed memory stores a number of micro-programs which areselectively executed on a time division basis. In one embodiment of thepresent invention, read-out of the memory is successively efiected foreach of the plural microprograms, at constant repetitive intervals, withthe micro-instructions so read-out being executed individually. Asequence control circuit is provided to determine the next address to beinterrogated in each micro-program from the result of the execution ofprior micro-instructions. Thus, the sequence control circuit decideswhether a jump or a sequential operation is to be performed next in aparticular micro-program and, accordingly provides the address of thenext micro-instruction to be read out. This next address is entered intothe system to access the next stored micro-instruction in thatparticular micro-program at an appropriate time interval. In thismanner, a single micro-program memory is shared for the concurrentexecution of a plurality of stored micro-programs on a time divisionbasis. Thus, while the individual microprograms are processed at thesame rate as in prior art control systems, the utilization of the memoryas a whole is improved in efficiently, thereby achieving the equivalentof high speed control.

The above and other objects, features and advantages of the inventionwill become apparent from the following description of an illustrativeembodiment thereof with reference to the drawings, in which:

FIG. I is a schematic diagram illustrating a prior art micro-programcontrol system;

FIG. 2 is a schematic diagram of the micro-program control systemaccording to one embodiment of the present invention;

FIG. 3 is a block diagram showing an example of an arithmetic unit usedin the system of FIG. 2,

FIG. 4 is a detailed wiring diagram showing an example of a sequencecontrol unit used in the system of FIG. 2, and

FIG. 5 is a timing chart illustrating the operation of the micro-programcontrol system of the invention. In the drawing, like referencenumerical designations in different figures identify like structuralelements.

Referring now to the drawing, and in particular to FIG. 1 thereof, thereis shown a typical micro-program control system of the prior art. Thesystem includes a fixed or semi-fixed memory 1 which storesmicro-programs. A selected micro-instruction, stored at an addressspecified by an address register 2, is read from the memory 1 into aread-out or output register 3. The micro-instruction in the register 3is transferred to an arithmetic unit 4 for execution, that is, toperform an arithmetic operation. The address information in the addressregister 2 is then supplied to an add-one" circuit 5 to augment theoriginal address by one. The updated address is then supplied to theaddress register 2 through an AND-gate 6 and an OR-gate 7. During a nextmemory 1 interrogation cycle, the information stored in the memory 1 atthe original address plus one is read out. In this manner,micro-instructions located in the memory I at immediately followingaddresses can be sequentially accessed.

In addition to such a sequential read-out, the system is subject to ajump or transfer operation. To provide discrimination of one from theother of these modes of operation, there is provided an AND-gate 9having a first input 8 and a second input 10. The first input 8 may beconnected with the arithmetic unit 4 to receive a signal indicatingwhether the result of the arithmetic operation performed is positive,negative or zero. Alternatively, it may be connected with a particularregister (not shown) associated with the system for detecting the stateof a particular bit therein. The second input 10 is connected to theread-out register 3 to detect the presence of jump or "transfer" bit inthis register.

When the conditions for a transfer are met, the AND-gate 9 produces abinary one output which is directly supplied to one input of an AND-gatel1 and to the other input of an AND-gate 6 after inversion. It will beseen that if the transfer condition is not met, the AND-gate 6 is openedto allow the passage of the output of the add-one circuit 5 to theOR-gate 7. Conversely, when the transfer condition is satisfied, theaddress stored in the output register 3 at that point in micro-programprocessing is fed through a terminal 12 to an AND-gate 13, or theinstruction code of the instruction read out from a main memory to beexecuted and the content of the address register 2 in which the mostsignificant bits are set to zero are supplied through a terminal 14 toAND-gate 15. This instruction code represents the address of a specifiedmicro-program to be read out next. To select an instruction from eitherthe terminal 12 or 14, a particular bit in the readout register 3 isdirectly supplied via a terminal 16 to the second input of the AND-gateand, after inversion, to the second input of AND-gate 13. An output fromthe selected AND-gate 15 or 13 is thus supplied to OR-gate 17 throughAND-gate 11 which is opened when the transfer condition is met.Accordingly, the transfer address data is supplied to the addressregister 2.

The effectiveness of a micro-program control system is predicated uponits ability to perform the conditional transfer function as well as toexecuting a program through successive read-out of sequential addresses.Where a conditional transfer is involved, the address for the nextmicro-instruction to be read out remains undetermined until the resultof an arithmetic operation is available, as mentioned above. Arelatively prolonged period of time is therefore required until theaddress for the next micro-instruction is decided as a result of theexecution of the preceding micro-instruction. Thus, execution of amicro-program sequence disadvantageously proceeds in a relatively slowmanner, even when a micro-program memory capable of high speed operationis used.

By contrast, in the micro-program control system of the invention asillustrated in H6. 2, information read from a memory 1 storing a numberof micro-program is supplied to a plurality of arithmetic operationcontrol units 4 at constant repetitive intervals, three such units 4a,4b and 4c being shown in FIG. 2. To this end, a switching gate 18 isconnected to the output of the memory 1, and a timing pulse signal froma pulse generator 191 is supplied to a ternary ring counter 19 so thatsuccessive cyclic gate signals may be obtained from three outputterminals 19a, 19b and 19c of the counter to distribute information readout from the memory 1 to the arithmetic units 4a, 4b and 4c in arepeated sequence.

In response to the results of arithmetic operations performed in thearithmetic units 4, a sequence control unit 20 is operable to decide thenext addresses to be accessed for the respective micro-programs, whichaddresses may be supplied through the address register 2 to the memory Iin synchronism with the switching operation of the switching gate 18 soas to correspond with the first, second and third micro-programs,respectively.

Each of the arithmetic units 40, 4b and 4c is not novel per se, but maybe of any conventional arrangement. In the example shown, the threeunits are assumed to be of an identical construction, one of these unitsbeing shown in detail in FlG. 3. With reference to FIG. 3, informationfrom two information buses 21 and 22 is supplied to an arithmeticcircuit 24 in which basic logical operations such as addition,subtraction, multiplication, shift or the like are performed, and thecomputational result is supplied by the circuit 24 to a bus 23. Ageneral purpose register 25 is provided and includes plural (forexample, 16 individual registers, which are separately specified byregister specifying circuits 26, 2'7 and 28. Read-out and write-inoperations are performed between the register specified by thespecifying circuit 26 and the bus 21 through gates 29 and 30,respectively. Similarly, read-out and writein operations are performedbetween the register specified by the specifying circuit 27 and the bus22 through gates 31 and 32, respectively, and information on the bus 23is written into the register specified by the specifying circuit 28through a gate 33.

A main memory is provided to store ordinary (MACRO) instructions anddata. One such instruction stored in the main memory 34 is executed byperforming a micro-program comprising a plurality of micro-instructions.When both gates 35 and 36 are open, information on the buses 21 and 22is stored in an address register 37 and in a write-in or input register38, respectively, for subsequently writing the content of the register38 into the main memory 34 at the address specified by the addressregister. In addition, when both gates 35 and 39 are open, informationat the address specified by the address register 37 are read through thegate 39 onto the bus 22. The control over the arithmetic circuit 24,specifying circuits 26, 27 and 28 and the gates 29, 30, 31, 32, 33, 35,36 and 39 is effected by information (micro-instructions) stored in acontrol register 40 associated with each arithmetic unit. The controlregister 40 is supplied with these micro-instructions read out from thememory 1 via the switching gate 18.

The bit arrangement of a micro-instruction, that is, the digital contentstored in the control register 40, is shown in Table 1 and comprisesforty bits. The first four hits of these represent by their combinationthe type of arithmetic operations (operation code) to be performed bythe arithmetic circuit 24. Specifically, in Table 1, the designation NOPrepresents no operation; BAD the binary addition of information on thebuses 21 and 22 and supply of the addition result to the bus 23, BSU thebinary subtraction between information on the buses 21 and 22 and supplyof the result to the bus 23; AND making a logical product of informationon the buses 21 and 22 and supply of the result to the bus 23; HADperforming a half-add (exclusive OR) operation in information and supplyof the result to the bus 23; OR making a logical sum of the informationand supply of its result to the bus 23; AD], AD2 and AD4 the addition ofl, 2 and 4, respectively to the information on the bus 21 and supply ofthe result to the bus 23; SB], S82 and 8B4 the subtraction of l, 2 and4, respectively, from the information on the bus 25 and supply of theresult to the bus 23; and SFI a ring shift, LSFT a shift to the left,and RSFT a shift to the right. The four bits in the portion 41A of thecontrol register 40 which represent the type of arithmetic operationsare supplied through lead wires 42 to the arithmetic circuits 24 tocondition it for the arithmetic operation specified.

TABLE -1 Type of Register Arith. specifying operation Gales circuitsTest Address Bit No. 1 4 5 13 14-17 18-2] 22-25 26-28 29-40 No. of

bits 4 9 4 4 4 3 12 bit controlled NC? No. gate No. 0 NO? 1 BAD 35 lUCJMP 2 BSU 6 39 2 ALLO 3 AND AND 7 36 3 4 HAD 8 43 4 5 OR 9 29 5 OVF 6AD] 30 6 carry 7 SB] 1 l 31 8 ADZ l2 32 9 532 I3 33 10 AD4 11 8B4 12SFl' l3 LSFT l4 RSFT IS A gate controlling portion 418 of the controlregister 40, which comprises nine bits from the fifth to thirteenth bit,is connected to control the gates 35, 39,36, 43,29,30,3l,32 and 33 inthe sequence of bit number, respectively, each bit separatelycontrolling a different gate. A gate 43 is provided (FIG. 4) todetermine whether the address stored in the address portion of thecontrol register 40 or a part of the information stored in the mainmemory 34 is to be used for a conditional transfer.

The bits from 14 to twenty-fifth bit, or those contained in a registerspecifying portion 41C of the control register 40, are used to specify aselected one of the 16 individual registers contained in the generalpurpose register 25. The first four bits in the specifying portion 41C(those numbered 14 to 17) are supplied in combination to the specifyingcircuit 26 to specify one of the i6 registers. The next four hits(numbered 18 to 21) are supplied to the specifying circuits 27 tospecify another register, and the last four bits (numbered 22 to 25) aresupplied to the specifying circuit 28 to specify a still different oneof the i6 registers.

The three bits numbered 26 to 28 in the control register 40 represent atest portion 41D thereof, the combination of these three hits providinga transfer condition. When this transfer condition coincides with theresult of an arithmetic operation performed in the arithmetic circuit24, the transfer condition is satisfied and a transfer operation iseffected. In the example shown, there are given six different transferconditions. NOP never satisfies such a condition, so that no transfer iseffected, UCJ MP represents the case where the condition is alwayssatisfied, and ALLO a transfer operation when the result of anarithmetic operation comprises bits which are all zeros. The symbolrepresents a transfer operation when the result of an arithmeticoperation has a positive polarity, and the symbol a transfer operationwhen the result of an arithmetic operation has a negative polarity. OVFrepresents a transfer operation when there is as overflow, and carry atransfer operation when there is a carry from the number of bitsallocated to one word. The remaining 12 bits numbered 29 to 40 of thecontrol register 40 constitute an address portion 41E which representsthe address to which the transfer is to be continued.

illustrative detail for the sequence control unit 20 of FIG. 2 is shownin FIG. 4. The control unit 20 specifies the next address when aconditional transfer is or is not effected depending upon the transfercondition in the read-out (control register) and upon the result ofarithmetic operations by a respective arithmetic units 40, 4b, or 40controlled by stored micro-instructions. The sequence control unit 20comprises three sequence control circuits 44a, 44b, and 44c, of anidentical construction, arranged in a manner corresponding to therespective arithmetic units 40, 4b and 40. It should be noted that areference character comprising a number followed by a letter such as a,b or c represents a component associated with different arithmetic unit40, 4b or 4c, respectively. Each circuit includes a register and isoperable to supply the address register 2 with either the address towhich transfer is to be continued, or a sequential address.

In each of the sequence control circuits 44a, 44b and 44c, informationfrom the common add-one circuit 5 is supplied to sequential addressingregisters 46a, 46b and 46c through AND-gates 45a, 45b and 45c,respectively. These registers are connected through AND-gates 47a, 47band 47c and ORgate 48a, 48b and 480, respectively, and through a commonOR-gate 49 with the address register 2.

The output from the address portion 41E of the respective controlregisters 40a, 40b and 40c associated with the arithmetic units 40, 4band 4c, respectively, are supplied to the terminals 12a, 12b and 120,and thence through AND-gates 13a, 13b and 13c and OR- gates 17a, 17b and17c, respectively, to AND-gates 50a, 50b and 50c, respectively. From thebuses 22c, 22b and 220 associated with the respective arithmetic units40, 4b and 4c, the instruction code portion of the information thereonis supplied to the terminals 14a, 14b and 14c, respectively, and thencethrough AND- gates 15a, 15b and 15c to the ORgates 17a, 17b and 17c,respectively. Gates 43a, 43b and 430 are con trolled by the fourth bitin the gate portion 418 of the respective control registers 40a, 40b and40c, and the output from these gates are directly applied to the otherinput of the AND-gates 15a, 15b and 15c and also applied, afterinversion, to the AND-gates 13a, 13b and 13c.

Thus it will be understood that when gate 430, for example, is opened,an instruction code (the instruction code of an instruction stored inthe main memory 340) is supplied from the bus 22a to the AND-gate 50a.On the other hand, when the gate 430 is closed, the content in theaddress portion 41E of the control register 40a is supplied to theAND-gate 50a.

A conditioning bit from the test portion 41D of the control register 40ais applied via a terminal a to one input of an AND-gate 9a, the otherinput of which receives an output from the arithmetic circuit 240through a terminal 80. The output of circuit 24a represents a particularstatus for the result of the arithmetic operation performed, that is,the status above in connection with the test portion 41D. When thearithmetic out-put coincides with the conditioning bit from the testportion 41D, i.e., when the transfer condition is met, the AND-gate 9aopens and its output is supplied to one input of the AND-gate 50a sothat when a timing pulse, discussed later, is furnished to its otherinput, the AND-gate 50a is opened, thereby allowing either the contentof the address portion 41E of the control register 400 or information onthe bus 22a to be supplied through the AND-gate 50a to the addressregister 2. The inverted output of the AND-gate 9a is connected to oneinput of the AND-gate 47a, so that when the transfer condition is notsatisfied, the content of the register 46a is supplied through thisANDgate 47a to the address register 2.

It will be appreciated that the sequence control circuits 44b and 440are similar in construction and operation to the sequence controlcircuit 440. Thus, these circuits include the AND-gates 9b and 9c which,like the AND-gate 9aare supplied with the output from the correspondingtest portion and the output from the respective arithmetic circuitswhich represents a particular status for the result of an arithmeticoperations performed thereby. The output of the AND-gate 9b and 9c aredirectly applied to the AND-gates 50b, 50c, and also applied, afterinversion, to the AND-gates 47b, 47c.

Output pulses repeatedly obtaining at a given interval from a terminal190 of the ring counter 19 are supplied to the AND-gates 45b, 47c and500. The output pulses from the counter terminal 19!) are supplied tothe AND-gates 45c, 47a and 50aand output pulses from the terminal 196are supplied to the AND-gates 45a, 47b and 50b. These AND-gates openonly when timing pulses from the terminals 19a, 19b and 19c are suppliedthereto. As shown, in FIG. 2 and 4, the content of the address register2 is adapted to be supplied to the micro-program memory 1, and to theadd-one circuit 5.

The pulse generator l9z produces pulses at times 1,, t t and so forth,as shown in FIG. 5A. The terminal 190 of the ring counter 19 providespulses at times t,, t, and so on, as shown in FIG. 5B, and the terminals19b and 19c provide pulses at times l l and so on, and at times t t andso on, respectively, as shown in FIGS. 5C and 5D. FIG. 5B depicts amicroinstruction 51a, for a first micro-program, having the bitarrangement set forth above, which is stored in the control register 40aat time t and which is read out at the time t,. The arithmetic circuit14a operates in accordance with the content of this micro-instruction(such an operation being symbolic shown at 520, of FIG. 5F), and at theend of the clock period beginning at t the matter of whether or not thetransfer condition (given by test register 40 portion 41D) is satisfiedis determined. When the transfer condition is satisfied, the status ofthe fourth gate bit in the gate portion 41B of the microinstruction 5laselectively conditions the gate 43a, thereby enabling the selectedAND-gate 150 or to pass the information on the bus 22a or the addressinformation in the address portion 41E of the micro-instruction 51a,therethrough and through the OR-gate 17a and AND-gate a to be stored inthe address register 20.

It should be understood that when the information is transmitted throughthe AND-gate 15a, an instruction code has previously been read out ontothe bus 22a from the memory 34. If the transfer condition is not met,the content of the register 46a is read out for storage in the addressregister 2. Such stored information for the address register 2 is shownat 53a in FIG. 5G. Further, at time a micro-instruction 51b, for thesecond micro-program is read out from the memory 1 into the controlregister 40b (FIG. 5H). It is noted that each register is arranged sothat the information entered at its input side appears at its outputside after a time delay of one clock period, this being effected by anyconventional gating or shifting circuitry.

At time the content 53a of the address register 2 is read out. A signal54a which comprises the address 53a plus one (effected by the add-onecircuit 5) is stored in the register 460 (FIG. SI). Correspondingly, asa consequence of the arithmetic operation 52b, (FIG. SJ) correspondingto execution of the micro-instruction 51b, from the control register40b, an address signal 53b, from the AND-gate 50b or 47b is stored inthe address register 2 at the end of the clock period beginning at Alsoa micro-instruction 51c, of the third micro-program is read out from thememory I and stored in the control register 40c (FIG. 5K).

At the next clock time the content 53!), of the address register 2 isread out, augmented by one by the circuit 5, and the resulting signal54b, stored in the register 46b (FIG. 5L). Also during this interval,the control register 400 is read out. Depending upon the result of thecorresponding arithmetic operation 520, (FIG. 5M), that is, dependingupon whether or not the transfer condition is satisfied, signal 53c,from either the AND-gate 50c or 47c is stored in the address register 2.While the above operations are being effected, the nextmicro-instruction 510 of the first micro-program is read out from thememory 1 and entered into the control register 400 (FIG. 5E).

During the following clock interval as a result of the arithmeticoperation 52a, for the micro-instruction Sla the output 53a from eitherAND gate 50a 47a is supplied to the address register 2 FIG. 56). Thedigital word 530, is read out from the address register 2, and thatinformation is supplemented by one in the manner discussed previously,with resulting signal being stored in the register 46c. Also,concurrently therewith, the next micro-instruction 5119 of the secondmicro-program is read out from the memory 1 and entered into the controlregister 4012 (FIG. 5H).

Similarly, at clock time t and as a result of the arithmetic operationsymbolically shown at 52b, for the micro-instruction Slb from thecontrol register 40b, the output 5%,. from either AND-gate 50b or 47b isstored in the address register 2. The information 53a, is read out fromthe address register 2, and after being increased by one, is stored inthe register 46a as 540,. Also during this clock interval, the nextmicro-instruction 51c, of the third micro-program is read into thecontrol register 40c. Such processing repeatedly continues in the abovedescribed manner.

Focusing on one micro-program, for example, the first micro-program, itwill be seen that the micro-instruction 51a, is read out at t, ("a um mt, (52d of FIG. F), and the results of this execution checked todetermine whether the transfer condition is satisfied. At clock time 1,,the address 53:1,, used to identify and read out the nextmicro-instruction 51a, of a program sequence, is supplied to the addressregister 2. This next instruction is read-out from the memory 1 at thenext clock time t,, and so on.

lt is observed that even if the memory 1 has a rapid cycle time whichcorresponds to a single time interval e.g., t,-t, or the like, a furtherperiod of time from I, to r, is required in order to fully execute themicro-instruction. This relatively long interval is necessary todetermine whether or not the transfer condition is met, and to thusdetermine the next address for execution. This means that the memory 1cannot be efficiently utilized to read out the next micro-instruction51a, of one micro-program immediately at the end of the clock periodbeginning at t,. To the contrary, the memory 1 must be left inoperativeduring the time interval from time t, to time :4. Such an inefficientmode of operation, employing only a single micro-program, hascharacterized prior art micro-program control systems. It will thereforebe appreciated that an increase in the operational speed of the memory 1does not result in a substantial improvement of the overall signalprocessing throughput rate.

However, in the micro-program control system according to the presentinvention, a plurality of microprograms or, in the present example, thefirst, second and third microprograms, are controlled in a time sharingmanner. When the micro-instruction 51a of the first micro-program hasbeen executed, the next address is stored in the address register 2.During the subsequent period of time before the next micro-instruction51a, of that program sequence is read out, the micro-instruction 518 ofthe second micro-program is read, followed by the micro-instruction Slcof the third micro-program. Thus, when the micro-instruction 51b of thesecond micro-program is executed and before the next micro-instruction51b, is read out, the micro-instruction 51c of the third micro-programis read out. Subsequently, the second micro-instruction 51a, of thefirst micro-program is read-out, and this process repeatedly continuesin similar fashion. In this manner, the memory 1 always reads-out amicro-instruction for one or another of the first, second and thirdmicro-programs during each clock cycle, thus achieving efficient memoryutilization.

in addition, since the multiple utilization of the micro-program memory1 is effected in a time sharing manner, with memory operation beingrepeated at a predetermined definite time interval, there is no need fora complex arrangement to check and obviate interruptions in thecomputing process, as is required for typical prior art multipleprogramming configurations.

The present system can be readily operated under the direction of arelatively simple executive control arrangement.

While three multiplexed micro-programs were employed in the embodimentdescribed above for purposes of illustration, any number more than onemay be utilized. It will be appreciated that this number can beincreased as the cycle time of the memory 1 becomes faster.

Also, the arithmetic units 40, 4b and 4e, illustrated as having anidentical construction, may in fact differ. These arithmetic units maybe controlled by different bit arrangements in the control registers 40.Further, a single memory 34 may be used for all of the micro-programs.In addition, as is apparent from the above description of systemoperation with reference to FIG. 5, the arithmetic operations performedduring execution of micro-instructions, as shown at 52],, 52b,, 520,3 5252b, are effected in successively offset period of time, so that onearithmetic circuit 24 may be shared by a plurality of micro-programs ina time division manner. ln this instance, registers such as generalpurpose registers 25 and control registers 40 may be separately providedfor each of the micro-programs.

The above system arrangement is merely illustrative of the principles ofthe present invention, numerous variations and adaptations thereof willbe readily apparent to those skilled in the art without departing fromthe spirit and scope of the present invention.

What is claimed:

1. A micro-program control system for electronic computing apparatus foreffecting data processing in time-shared fashion in accordance with apreselected number of micro-programs comprising:

a memory having at least said preselected number of micro-programsstored therein,

an address register,

timing means for cyclically controlling said ap paratus for said pluralmicro-programs,

a plurality of output registers controlled by said timing means forstoring micro'instructions for said respective micro-programs, read outfrom said memory at the memory addresses cyclically identified by thecontents of said address register,

first address updating means for providing a first next instructionaddress based on the memory address identified by the current contentsof said address register,

a plurality of additional registers for said respective micro-programs,

gate means controlled by said timing means for loading said additionalregisters with the first next instruction addresses for said respectivemicro-programs,

second address updating means for selectively providing in response to amicro-instruction stored in each of said output registers, a second nextinstruction address based on one of the prior processedmicro-instructions and the instruction obtained as a result of previousdata processing, and control gating means controlled by said timingmeans and a logical combination of the priorprocessed micro-instructionand the result of data processing effected in accordance therewith forloading said address register with either of said first next instructionaddress and the selected second next instruction address.

2. A micro-program control system as in claim 1 wherein said firstaddress updating means adds a fixed increment to the current contents ofsaid address register.

3. A micro-program control system as in claim 1 further comprisingarithmetic means controlled by the contents of an associated one of saidoutput registers, and means responsive to signals characterizing saidarithmetic means for selectively signaling the incidence of a programinstruction transfer condition for a selected one of the storedmicro-programs, said signaling means having the output thereof connectedto said control gating means.

4. A micro-program control system as in claim 1 further comprisingplural arithmetic means, said output registers being respectivelyassociated with said arithmetic means, each of said output registershaving a first portion thereof connected to the corresponding arithmeticmeans for defining the functional operation performed thereby, a secondportion thereof for selectively identifying a transfer operation, and athird portion thereof containing an address in said memory, said controlgating means including logic means connected to each of said arithmeticmeans and its associated output register for selecting between saidfirst and second next instruction address from each micro-program.

5. A micro-program control system as in claim 4 wherein the contents ofsaid address portion of each of said output registers is supplied as aninput signal to said second address updating means.

6. A combination as in claim 5 further comprising additional memorymeans, and means for selectively connecting the contents of saidadditional memory means as an input signal to said second addressupdating means.

7. A combination as in claim 6 wherein said second address updatingmeans comprises plural next address selecting circuit means eachassociated with a different micro-program, each next address selectingcircuit means including first and second coincidence means forselectively passing said first next instruction address or said secondnext instruction address respectively, one of said first and secondcoincidence means being opened during a selected cyclically repeatingtime interval by said timing means, logic means for enabling a selectedone of said first or second coincidence means responsive to the presenceor absence of micro-instruction transfer requirement, means forsupplying a selected second next instruction address to said secondcoincidence means, means for supplying said first next instructionaddress to said first coincidence means.

8. A combination as in claim 7 further comprising disjunctive logicmeans for connecting the outputs of said first and second coincidencemeans for each of said next address selecting circuit means with saidaddress register.

9. A micro-program control system as in claim 1 wherein said timingmeans comprise a pulse generator, and plural stage ring counter meanshaving a clock input thereof connected to said pulse generator, theoutputs from the several stages of said ring counters means beingdistributed to said control gating means.

0 A micro-program control system as in claim 4 further comprisingswitched gate means controlled by said timing means for selectivelydistributing the mic roinstructions read out from said memory to saidoutput registers associated with said arithmetic means.

11. A method for effecting micro-program control of electronic computingapparatus which includes a memory, an address register, an addressupdating circuit, plural arithmetic circuits and timing circuitry forcyclically subdividing the control of said computing apparatus into aplurality of clock phases depending upon the number of micro-programs tobe simultaneously executed on a time shared basis, comprising the stepsof reading out a micro-program instruction for a first one of saidmicro-programs being executed during each clock phase, effectingexecution during that clock phase of an instruction for a secondmicro-program read from the memory during a preceding clock phase, andimpressing a next address for a third one of the micro-programs in saidaddress register during that clock phase, said address representing aselection between a sequential updating of the previous address for saidthird micro-program and a transfer for said third micro-program, saidmemory thereby being interrogated to read out a new micro-instructionduring each clock phase.

1. A micro-program control system for electronic computing apparatus foreffecting data processing in time-shared fashion in accordance with apreselected number of micro-programs comprising: a memory having atleast said preselected number of microprograms stored therein, anaddress register, timing means for cyclically controlling said apparatusfor said plural micro-programs, a plurality of output registerscontrolled by said timing means for storing micro-instructions for saidrespective microprograms, read out from said memory at the memoryaddresses cyclically identified by the contents of said addressregister, first address updating means for providing a first nextinstruction address based on the memory address identified by thecurrent contents of said address register, a plurality of additionalregisters for said respective microprograms, gate means controlled bysaid timing means for loading said additional registers with the firstnext instruction addresses for said respective micro-programs, secondaddress updating means for selectively providing in response to amicro-instruction stored in each of said output registers, a second nextinstruction address based on one of the prior processedmicro-instructions and the instruction obtained as a result of previousdata processing, and control gating means controlled by said timingmeans and a logical combination of the prior-processed micro-instructionand the result of data processing effected in accordance therewith forloading said address register with either of said first next instructionaddress and the selected second next instruction address.
 2. Amicro-program control system as in claim 1 wherein said first addressupdating means adds a fixed increment to the current contents of saidaddress register.
 3. A micro-program control system as in claim 1further comprising arithmetic means controlled by the contents of anassociated one of said output registers, and means responsive to signalscharacterizing said arithmetic means for selectively signaling theincidence of a program instruction transfer condition for a selected oneof the stored micro-programs, said signaling means having the outputthereof connected to said control gating means.
 4. A micro-programcontrol system as in claim 1 further comprising plural arithmetic means,said output registers being respectively associated with said arithmeticmeans, each of said output registers having a first portion thereofconnected to the corresponding arithmetic means for defining thefunctional operation performed thereby, a second portion thereof forselectively identifying a transfer operation, and a third portionthereof containing an address in said memory, said control gating meansincluding logic means connected to each of said arithmetic means and itsassociated output register for selecting between said first and secondnext instruction address from each micro-program.
 5. A micro-programcontrol system as in claim 4 wherein the contents of said addressportion of each of said output registers is supplied as an input signalto said second address updating means.
 6. A combination as in claim 5further comprising additional memory means, and means for selectivelyconnecting the contents of said additional memory means as an inputsignal to said second address updating means.
 7. A combination as inclaim 6 wherein said second address updating means comprises plural nextaddress selecting circuit means each associated with a differentmicro-program, each next address selecting circuit means including firstand second coincidence means for selectively passing said first nextinstruction address or said second next instruction addressrespectively, one of said first and second coincidence means beingopened during a selected cyclically repeating time interval by saidtiming means, logic means for enabling a selected one of said first orsecond coincidence means responsive to the presence or absence ofmicro-instruction transfer requirement, means for supplying a selectedsecond next instruction address to said second coincidence means, meansfor supplying said first next instruction address to said firstcoincidence means.
 8. A combination as in claim 7 further comprisingdisjunctive logic means for connecting the outputs of said first andsecond coincidence means for each of said next address selecting circuitmeans with said address register.
 9. A micro-program control system asin claim 1 wherein said timing means cOmprise a pulse generator, andplural stage ring counter means having a clock input thereof connectedto said pulse generator, the outputs from the several stages of saidring counters means being distributed to said control gating means. 10.A micro-program control system as in claim 4 further comprising switchedgate means controlled by said timing means for selectively distributingthe micro-instructions read out from said memory to said outputregisters associated with said arithmetic means.
 11. A method foreffecting micro-program control of electronic computing apparatus whichincludes a memory, an address register, an address updating circuit,plural arithmetic circuits and timing circuitry for cyclicallysubdividing the control of said computing apparatus into a plurality ofclock phases depending upon the number of micro-programs to besimultaneously executed on a time shared basis, comprising the steps ofreading out a micro-program instruction for a first one of saidmicro-programs being executed during each clock phase, effectingexecution during that clock phase of an instruction for a secondmicro-program read from the memory during a preceding clock phase, andimpressing a next address for a third one of the micro-programs in saidaddress register during that clock phase, said address representing aselection between a sequential updating of the previous address for saidthird micro-program and a transfer for said third micro-program, saidmemory thereby being interrogated to read out a new micro-instructionduring each clock phase.